Electronic circuits often use a clock signal to control the timing of various operations. For example, the sampling of a data signal can be triggered according to the rising and/or falling edges of a clock signal.
In an electronic system, certain characteristics (such as duty cycle, phase and timing, etc.) of clock signals may be affected by jitter, by skew caused by circuitry in the electronic system, by circuit aging, by temperature changes, by a variety of different noise sources, by process variations in the elements that are present in the electronic system, or by other factors. These factors can thus cause a clock signal to be defective or otherwise non-ideal in that the clock signal may have a less-than-optimum duty cycle, phase or timing, etc.
The defective nature of the clock signal can in turn cause erroneous operation in the electronic system. For example, data sampling that is performed according to the defective clock signal can cause the data signal to be erroneously read (e.g., missed samples, extra samples, irregular sampling, etc.).